SC16C2552B Datasheet, PDF (20/38 Pages) NXP Semiconductors – 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

NXP Semiconductors
SC16C2552B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.8 Modem Status Register (MSR)
This register provides the current state of the control interface signals from the modem or
other peripheral device to which the SC16C2552B is connected. Four bits of this register
are used to indicate the changed information. These bits are set to a logic 1 whenever a
control input from the modem changes state. These bits are set to a logic 0 whenever the
CPU reads this register.
Table 18. Modem Status Register bits description
Bit Symbol Description
7
MSR[7] Carrier Detect, CD. During normal operation, this bit is the complement of the
CD input. Reading this bit in the Loopback mode produces the state of
MCR[3] (OP2A/OP2B).
6
MSR[6] Ring Indicator, RI. During normal operation, this bit is the complement of the
RI input. Reading this bit in the Loopback mode produces the state of
MCR[2] (OP1A/OP2A).
5
MSR[5] Data Set Ready, DSR. During normal operation, this bit is the complement of
the DSR input. During the Loopback mode, this bit is equivalent to MCR[0]
(DTR).
4
MSR[4] Clear To Send, CTS. During normal operation, this bit is the complement of
the CTS input. During the Loopback mode, this bit is equivalent to MCR[1]
(RTS).
3
MSR[3] ∆CD ^[1]
logic 0 = no CD change (normal default condition)
logic 1 = the CD input to the SC16C2552B has changed state since the
last time it was read. A modem Status Interrupt will be generated.
2
MSR[2] ∆RI ^[1]
logic 0 = no RI change (normal default condition)
logic 1 = the RI input to the SC16C2552B has changed from a logic 0 to a
logic 1. A modem Status Interrupt will be generated.
1
MSR[1] ∆DSR ^[1]
logic 0 = no DSR change (normal default condition)
logic 1 = the DSR input to the SC16C2552B has changed state since the
last time it was read. A modem Status Interrupt will be generated.
0
MSR[0] ∆CTS ^[1]
logic 0 = no CTS change (normal default condition)
logic 1 = the CTS input to the SC16C2552B has changed state since the
last time it was read. A modem Status Interrupt will be generated.
[1] Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated.
SC16C2552B_3
Product data sheet
Rev. 03 — 12 February 2009
© NXP B.V. 2009. All rights reserved.
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