SC16C2552B Datasheet, PDF(1/38 Page) NXP Semiconductors – 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

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SC16C2552B Datasheet, PDF (1/38 Pages) NXP Semiconductors – 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

SC16C2552B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte

FIFOs

Rev. 03 â 12 February 2009

Product data sheet

1. General description

The SC16C2552B is a two channel Universal Asynchronous Receiver and Transmitter

(UART) used for serial data communications. Its principal function is to convert parallel

data into serial data, and vice versa. The UART can handle serial data rates up to

5 Mbit/s.

The SC16C2552B is pin compatible with the PC16552 and ST16C2552. The

SC16C2552B provides enhanced UART functions with 16-byte FIFOs, modem control

interface, DMA mode data transfer and concurrent writes to control registers of both

channels. The DMA mode data transfer is controlled by the FIFO trigger levels and the

RXRDY and TXRDY signals. On-board status registers provide the user with error

indications and operational status. System interrupts and modem control features may be

tailored by software to meet speciï¬c user requirements. An internal loopback capability

allows on-board diagnostics. Independent programmable baud rate generators are

provided to select transmit and receive baud rates.

The SC16C2552B operates at 5 V, 3.3 V and 2.5 V and the industrial temperature range,

and is available in a plastic PLCC44 package.

2. Features

I Industrial temperature range (â40 Â°C to +85 Â°C)

I 5 V, 3.3 V and 2.5 V operation

I Pin-to-pin compatible to PC16C552, ST16C2552

I Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V

I 5 V tolerant on input only pins1

I 16-byte transmit FIFO

I 16-byte receive FIFO with error ï¬ags

I Independent transmit and receive UART control

I Four selectable receive FIFO interrupt trigger levels; ï¬xed transmit FIFO interrupt

trigger level

I Modem control functions (CTS, RTS, DSR, DTR, RI, CD)

I DMA operation and DMA monitoring via package I/O pins, TXRDY/RXRDY

I UART internal register sections A and B may be written to concurrently

I Multi-function output allows more package functions with fewer I/O pins

I Programmable character lengths (5, 6, 7, 8), with even, odd, or no parity

1. For data bus pins D7 to D0, see Table 23 âLimiting valuesâ.

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