PSMN3R5-30YL_09 Datasheet, PDF (2/14 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

NXP Semiconductors
PSMN3R5-30YL
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2. Pinning information
Pin
Symbol Description
1
S
source
2
S
source
3
S
source
4
G
gate
mb
D
mounting base; connected to
drain
3. Ordering information
Simplified outline
mb
1234
SOT669 (LFPAK)
Graphic symbol
D
G
mbb076 S
Table 3. Ordering information
Type number
Package
Name
Description
PSMN3R5-30YL LFPAK
plastic single-ended surface-mounted package (LFPAK); 4 leads
4. Limiting values
Version
SOT669
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
V_DS
drain-source voltage T_j ≥ 25 °C; T_j ≤ 175 °C
V_DGR
drain-gate voltage
T_j ≥ 25 °C; T_j ≤ 175 °C; R_GS = 20 kΩ
V_GS
gate-source voltage
I_D
drain current
V_GS = 10 V; T_mb = 100 °C; see Figure 1
[1]
V_GS = 10 V; T_mb = 25 °C; see Figure 1
[1]
I_DM
peak drain current
t_p ≤ 10 µs; pulsed; T_mb = 25 °C; see Figure 3
P_tot
total power dissipation T_mb = 25 °C; see Figure 2
T_stg
storage temperature
T_j
junction temperature
Source-drain diode
I_S
source current
T_mb = 25 °C;
[1]
I_SM
peak source current t_p ≤ 10 µs; pulsed; T_mb = 25 °C
Avalanche ruggedness
E_DS(AL)S
non-repetitive
V_GS = 10 V; T_j(init) = 25 °C; I_D = 100 A; V_sup ≤ 30 V;
drain-source avalanche R_GS = 50 Ω; unclamped
energy
[1] Continuous current is limited by package.
Min Max Unit
-
30
V
-
30
V
-20 20
V
-
86
A
-
100 A
-
447 A
-
74
W
-55 175 °C
-55 175 °C
-
100 A
-
447 A
-
54
mJ
PSMN3R5-30YL_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 31 December 2009
© NXP B.V. 2009. All rights reserved.
2 of 14