BUJ100LR Datasheet, PDF (2/11 Pages) NXP Semiconductors – Silicon diffused power transistor

NXP Semiconductors
BUJ100LR
Silicon diffused power transistor
2. Pinning information
Table 2. Pinning information
Pin
Symbol Description
1
B
base
2
C
collector
3
E
emitter
3. Ordering information
Simplified outline
321
SOT54
(TO-92)
Graphic symbol
C
B
E
sym123
Table 3. Ordering information
Type number
Package
Name
Description
BUJ100LR
TO-92
plastic single-ended leaded (through hole) package; 3 leads
4. Limiting values
Version
SOT54
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
V_CESM
collector-emitter peak V_BE = 0 V
voltage
V_CBO
V_CEO
collector-base voltage
collector-emitter
voltage
I_E = 0 A
I_B = 0 A
I_C
I_CM
I_B
I_BM
P_tot
T_stg
T_j
V_EBO
collector current
peak collector current
base current
peak base current
total power dissipation
storage temperature
junction temperature
emitter-base voltage
DC; see Figure 1
T_lead ≤ 25 °C; see Figure 2
I_C = 0 A; I(Emitter) = 10 mA
Min Max Unit
-
700 V
-
700 V
-
400 V
-
1
A
-
2
A
-
0.5 A
-
1
A
-
2.1 W
-65 150 °C
-
150 °C
-
9
V
BUJ100LR_1
Product data sheet
Rev. 01 — 12 August 2009
© NXP B.V. 2009. All rights reserved.
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