74HC00 Datasheet, PDF (2/15 Pages) NXP Semiconductors – Quad 2-input NAND gate

NXP Semiconductors
4. Functional diagram
74HC00; 74HCT00
Quad 2-input NAND gate
1 1A
2 1B
4 2A
5 2B
9 3A
10 3B
12 4A
13 4B
1Y 3
2Y 6
3Y 8
4Y 11
mna212
Fig 1. Logic symbol
1
2
&
3
4
5
&
6
9
10
&
8
12
13
&
11
mna246
Fig 2. IEC logic symbol
5. Pinning information
5.1 Pinning
A
Y
B
mna211
Fig 3. Logic diagram (one gate)
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
74HC00
74HCT00
14 V_CC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
001aal323
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14
74HC00
74HCT00
terminal 1
index area
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND⁽¹⁾
13 4B
12 4A
11 4Y
10 3B
9 3A
001aal324
Transparent top view
(1) The substrate is attached to this pad using conductive
die attach material. It can not be used as supply pin or
input. It is recommended that no connection is made at
all.
Fig 5. Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
V_CC
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
74HC_HCT00_4
Product data sheet
Description
data input
data input
data output
ground (0 V)
supply voltage
Rev. 04 — 11 January 2010
© NXP B.V. 2010. All rights reserved.
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