SC16C550B Datasheet, PDF (19/48 Pages) NXP Semiconductors – 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs

NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR)
The serial transmitter section consists of an 8-bit Transmit Holding Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D[7:0]) to the
THR, providing that the THR or TSR is empty. The THR empty flag in the LSR register will
be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR.
Note that a write operation can be performed when the THR empty flag is set
(logic 0 = FIFO full; logic 1 = at least one FIFO location available).
The serial receive section also contains an 8-bit Receive Holding Register (RHR).
Receive data is removed from the SC16C550B and receive FIFO by reading the RHR
register. The receive section provides a mechanism to prevent false starts. On the falling
edge of a start or false start bit, an internal receiver counter starts counting clocks at the
16× clock rate. After 7¹â„₂ clocks, the start bit time should be shifted to the center of the
start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated.
Evaluating the start bit in this manner prevents the receiver from assembling a false
character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INT output pin.
Table 10. Interrupt Enable Register bits description
Bit Symbol Description
7:4 IER[7:4] not used
3 IER[3] Modem Status Interrupt.
logic 0 = disable the modem status register interrupt (normal default
condition)
logic 1 = enable the modem status register interrupt
2 IER[2] Receive Line Status interrupt. This interrupt will be issued whenever a fully
assembled receive character is transferred from RSR to the RHR/FIFO, that is,
data ready, LSR[0].
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
1 IER[1] Transmit Holding Register interrupt. This interrupt will be issued whenever the
THR is empty, and is associated with LSR[1].
logic 0 = disable the transmitter empty interrupt (normal default condition)
logic 1 = enable the transmitter empty interrupt
0 IER[0] Receive Holding Register interrupt. This interrupt will be issued when the FIFO
has reached the programmed trigger level, or is cleared when the FIFO drops
below the trigger level in the FIFO mode of operation.
logic 0 = disable the receiver ready interrupt (normal default condition)
logic 1 = enable the receiver ready interrupt
SC16C550B_5
Product data sheet
Rev. 05 — 1 October 2008
© NXP B.V. 2008. All rights reserved.
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