SC16C550B Datasheet, PDF(1/48 Page) NXP Semiconductors – 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs

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SC16C550B Datasheet, PDF (1/48 Pages) NXP Semiconductors – 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs

SC16C550B

5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs

Rev. 05 â 1 October 2008

Product data sheet

1. General description

The SC16C550B is a Universal Asynchronous Receiver and Transmitter (UART) used for

serial data communications. Its principal function is to convert parallel data into serial

data, and vice versa. The UART can handle serial data rates up to 3 Mbit/s.

The SC16C550B is pin compatible with the ST16C550, TL16C550 and PC16C550, and it

will power-up to be functionally equivalent to the 16C450. The SC16C550B also provides

DMA mode data transfers through FIFO trigger levels and the TXRDY and RXRDY signals

(TXRDY and RXRDY are not supported in the HVQFN32 package). On-board status

registers provide the user with error indications, operational status, and modem interface

control. System interrupts may be tailored to meet user requirements. An internal

loopback capability allows on-board diagnostics.

The SC16C550B operates at 5 V, 3.3 V and 2.5 V, and the Industrial temperature range,

and is available in plastic HVQFN32, DIP40, PLCC44 and LQFP48 packages.

2. Features

I 5 V, 3.3 V and 2.5 V operation

I Industrial temperature range

I After reset, all registers are identical to the typical 16C450 register set

I Capable of running with all existing generic 16C450 software

I Pin compatibility with the industry-standard ST16C450/550, TL16C450/550,

PC16C450/550

I Up to 3 Mbit/s transmit/receive operation at 5 V, 2 Mbit/s at 3.3 V, and 1 Mbit/s at 2.5 V

I 5 V tolerant on input only pins1

I 16 byte transmit FIFO

I 16 byte receive FIFO with error ï¬ags

I Programmable auto-RTS and auto-CTS

N In auto-CTS mode, CTS controls transmitter

N In auto-RTS mode, RX FIFO contents and threshold control RTS

I Automatic hardware ï¬ow control

I Software selectable baud rate generator

I Four selectable Receive FIFO interrupt trigger levels

I Standard modem interface

I Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break)

I Independent receiver clock input

I Transmit, Receive, Line Status, and Data Set interrupts independently controlled

1. For data bus pins D7 to D0, see Table 24 âLimiting valuesâ.

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