PN7360AUHN Datasheet, PDF (15/86 Pages) NXP Semiconductors – NFC Cortex-M0 microcontroller

NXP Semiconductors
PN746X_736X
NFC Cortex-M0 microcontroller
8.4 GPIOs
The PN7462 has 12 general-purpose I/O (GPIO) with configurable pull-up and pull-down
resistors, plus nine additional GPIOs multiplexed with SPI master, I²C-bus master and
AUX pins.
Pins can be dynamically configured as inputs or outputs. GPIO read/write are made by the
FW using dedicated registers that allow reading, setting or clearing inputs. The value of
the output register can be read back, as well as the current state of the input pins.
8.4.1 GPIO features
• Dynamic configuration as input or output
• 3.3 V and 1.8 V signaling
• Programmable weak pull-up and weak pull-down
• Independent interrupts for GPIO1 to GPIO12
• Interrupts: edge or level sensitive
• GPIO1 to GPIO12 can be programmed as wake-up sources
• Programmable spike filter (3 ns)
• Programmable slew rate (3 ns and 10 ns)
• Hysteresis receiver with disable option
8.4.2 GPIO configuration
The GPIO configuration is done through the PCR module (power, clock, and reset).
8.4.3 GPIO interrupts
GPIO1 to GPIO12 can be programmed to generate an interrupt on a level, a rising or
falling edge or both.
8.5 CRC engine 16/32 bits
The PN7462 has a configurable 16/32-bit parallel CRC co-processor.
The 16-bit CRC is compliant to X.25 (CRC-CCITT, ISO/IEC 13239) standard with a
generator polynome of:
gx = x¹⁶ + x¹² + x⁵ + 1
The 32-bit CRC is compliant to the ethernet/AAL5 (IEEE 802.3) standard with a generator
polynome of:
gx = x³² + x²⁶ + x²³ + x²² + x¹⁶ + x¹² + x¹¹ + x¹⁰ + x⁸ + x⁷ + x⁵ + x⁴ + x² + x + 1
CRC calculation is performed in parallel, meaning that one CRC calculation is performed
in one clock cycle. The standard CRC 32 polynome is compliant with FIPS140-2.
Note: No final XOR calculation is performed.
Following are the CRC engine features:
• Configurable CRC preset value
• Selectable LSB or MSB first
PN746X_736X
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.1 — 5 April 2016
369231
© NXP Semiconductors N.V. 2016. All rights reserved.
15 of 86