PCF8563 Datasheet, PDF (15/32 Pages) NXP Semiconductors – Real-time clock/calendar

NXP Semiconductors
PCF8563
Real-time clock/calendar
data output
by transmitter
data output
by receiver
SCL from
master
S
1
2
START
condition
Fig 12. Acknowledgement on the I²C-bus
not acknowledge
acknowledge
8
9
clock pulse for
acknowledgement
mbc 602
8.5 I²C-bus protocol
8.5.1 Addressing
Before any data is transmitted on the I²C-bus, the device which should respond is
addressed first. The addressing is always carried out with the first byte transmitted after
the start procedure.
The PCF8563 acts as a slave receiver or slave transmitter. Therefore the clock signal SCL
is only an input signal, but the data signal SDA is a bidirectional line.
The PCF8563 slave address is shown in Figure 13.
1 0 1 0 0 0 1 R/W
Fig 13. Slave address
group 1
group 2
mce189
8.5.2 Clock/calendar read/write cycles
The I²C-bus configuration for the different PCF8563 read and write cycles is shown in
Figure 14, Figure 15 and Figure 16. The word address is a 4-bit value that defines which
register is to be accessed next. The upper four bits of the word address are not used.
PCF8563_6
Product data sheet
Rev. 06 — 21 February 2008
© NXP B.V. 2008. All rights reserved.
15 of 32