PCF8563 Datasheet, PDF (13/32 Pages) NXP Semiconductors – Real-time clock/calendar

NXP Semiconductors
PCF8563
Real-time clock/calendar
Table 25. Register reset value^[1] …continued
Address Register name Bit 7 Bit 6
05h
days
x
x
06h
weekdays
x
x
07h
century_months x
x
08h
years
x
x
09h
minute_alarm
1
x
0Ah
hour_alarm
1
x
0Bh
day_alarm
1
x
0Ch
weekday_alarm 1
x
0Dh
CLKOUT_control 1
x
0Eh
timer_control
0
x
0Fh
timer
x
x
Bit 5
x
x
x
x
x
x
x
x
x
x
x
Bit 4
x
x
x
x
x
x
x
x
x
x
x
Bit 3
x
x
x
x
x
x
x
x
x
x
x
Bit 2
x
x
x
x
x
x
x
x
x
x
x
Bit 1
x
x
x
x
x
x
x
x
0
1
x
Bit 0
x
x
x
x
x
x
x
x
0
1
x
[1] registers marked ‘x’ are undefined at power-up and unchanged by subsequent resets.
8. Characteristics of the I²C-bus
The I²C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see Figure 9).
SDA
SCL
Fig 9. Bit transfer
data line
stable;
data valid
change
of data
allowed
mbc 621
8.2 Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P); see Figure 10.
PCF8563_6
Product data sheet
Rev. 06 — 21 February 2008
© NXP B.V. 2008. All rights reserved.
13 of 32