TDA8920C_09 Datasheet, PDF (14/39 Pages) NXP Semiconductors – 2 ´ 110 W class-D power amplifier

NXP Semiconductors
TDA8920C
2 × 110 W class-D power amplifier
V_O (V)
V_{O(offset)(on)}
Standby
V_{O(offset)(mute)}
slope is directly related to the time-constant
of the RC network on the MODE pin
Mute
On
0
0.8
2.2
3.0
Fig 8. Behavior of mode selection pin MODE
12. Dynamic characteristics
4.2
5.5
V_MODE (V)
coa021
12.1 Switching characteristics
Table 9. Dynamic characteristics
V_P[1] = ±30 V; T_amb = 25 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Internal oscillator
f_osc(typ)
typical oscillator frequency R_OSC = 30.0 kΩ
290
345
365
kHz
f_osc
oscillator frequency
250
-
450
kHz
External oscillator input or frequency tracking; pin OSC
V_OSC
V_trip
f_track
Z_i
C_i
t_r(i)
voltage on pin OSC
trip voltage
tracking frequency
input impedance
input capacitance
input rise time
HIGH-level
SGND + 4.5 SGND + 5
SGND + 6 V
-
SGND + 2.5 -
V
[2] ₅₀₀
-
900
kHz
1
-
-
MΩ
-
-
15
pF
from SGND + 0 V to ^[3] -
-
100
ns
SGND + 5 V
[1] V_P is the supply voltage on pins VDDP1, VDDP2 and VDDA.
[2] When using an external oscillator, the frequency f_track (500 kHz minimum, 900 kHz maximum) will result in a PWM frequency f_osc
(250 kHz minimum, 450 kHz maximum) due to the internal clock divider; see Section 8.2.
[3] When t_r(i) > 100 ns, the output noise floor will increase.
TDA8920C_2
Product data sheet
Rev. 02 — 11 June 2009
© NXP B.V. 2009. All rights reserved.
14 of 39