SA58646 Datasheet, PDF (14/42 Pages) NXP Semiconductors – UHF 900 MHz transceiver IC

NXP Semiconductors
SA58646
UHF 900 MHz transceiver IC
7.7 Other features
7.7.1 Voltage regulator
Regulator voltage VREG is the internal supply for the RX and TX PLLs. It is regulated at
2.7 V nominal voltage. Two capacitors with 4.7 µF and 100 nF values must be connected
to pin VREG to filter and stabilize this regulated voltage. The tolerance of the regulated
voltage is initially ±8 % but is improved to ±2 % after the internal band gap voltage
reference is adjusted via the microcontroller interface. In Inactive mode, the regulator
voltage adjustment is automatically disabled.
7.7.2 Low battery detector
The low battery detector measures the supply voltage V_CC with a resistor divider and a
comparator. One input of the comparator is connected to reference voltage VB and the
other is connected to the middle point of the resistor divider. To prevent spurious switching
the comparator has a built-in hysteresis. The precision of the detection depends on the
divider accuracy, the comparator offset and the accuracy of the reference voltage. The
output is multiplexed at pin CDLBD. When the battery voltage level is under the threshold
voltage, the CDLBD output is set at LOW level.
7.8 Microcontroller serial interface
The serial interface is used for programming the IC. To program the IC, 19 bits are used:
16 bits for data and 3 bits for register addresses. The serial interface requires 3 pins:
DATA, CLK, EN (see Figure 10).
The serial interface pins are supplied by regulator voltage VREG. The ESD protection
diodes on these pins are connected to the supply voltage V_CC. Digital outputs (CDLBD
and DATAO) have open-collector or open-drain; CLKO is an emitter-follower output.
The DATA, CLK and EN pins provide a 3-wire unidirectional serial interface for
programming the reference counters, the transmit and receive channel divider counters,
and the control functions.
The interface consists of 19-bit shift registers connected to a matrix of registers organized
as 7 words of 16 bits (all control registers). The data is entered with the most significant bit
first. The leading 16 bits include the data (D15 to D0), while the trailing 3 bits set up the
address (AD2 to AD0). The first bit entered is D15, the last bit AD0.
The DATA and CLK pins are used to load data into the shift registers. Data is clocked into
the shift registers on negative clock transitions.
A new clock divider ratio is enabled thanks to an extra EN rising edge. Minimum hold time
is 50 ns. During that time, no clock cycle is allowed. These extra EN edges can be applied
to all the data programmed, but will have no effect on the serial interface programming.
8. Data registers and addresses
D15 is the most significant bit, and is written first. Table 7 shows the data latches and
addresses which are used to select each of the registers.
SA58646_1
Product data sheet
Rev. 01 — 8 February 2007
© NXP B.V. 2007. All rights reserved.
14 of 42