74HC373BQ Datasheet, PDF (14/26 Pages) NXP Semiconductors – Octal D-type transparent latch; 3-state

NXP Semiconductors
74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Table 9. Dynamic characteristics 74HCT373 …continued
Voltages are referenced to GND (ground = 0 V); C_L = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
Min Typ Max Unit
T_amb = 40 C to +85 C
t_pd
propagation delay
Dn to Qn; see Figure 8
[1]
V_CC = 4.5 V
-
-
38
ns
LE to Qn; see Figure 9
t_en
enable time
V_CC = 4.5 V
OE to Qn; see Figure 10
-
-
40
ns
[2]
t_dis
disable time
V_CC = 4.5 V
OE to Qn; see Figure 10
-
-
40
ns
[3]
t_t
transition time
V_CC = 4.5 V
-
-
38
ns
Qn; see Figure 8 and Figure 9
[4]
V_CC = 4.5 V
-
-
15
ns
t_W
pulse width
LE HIGH; see Figure 9
V_CC = 4.5 V
20
-
-
ns
t_su
set-up time
Dn to LE; see Figure 11
t_h
hold time
V_CC = 4.5 V
Dn to LE; see Figure 11
15
-
-
ns
T_amb = 40 C to +125 C
t_pd
propagation delay
V_CC = 4.5 V
Dn to Qn; see Figure 8
4
-
-
ns
[1]
V_CC = 4.5 V
-
-
45
ns
LE to Qn; see Figure 9
t_en
enable time
V_CC = 4.5 V
OE to Qn; see Figure 10
-
-
48
ns
[2]
t_dis
disable time
V_CC = 4.5 V
OE to Qn; see Figure 10
-
-
48
ns
[3]
t_t
transition time
V_CC = 4.5 V
-
-
45
ns
Qn; see Figure 8 and Figure 9
[4]
V_CC = 4.5 V
-
-
18
ns
t_W
pulse width
LE HIGH; see Figure 9
V_CC = 4.5 V
24
-
-
ns
t_su
set-up time Dn to LE
Dn to LE; see Figure 11
V_CC = 4.5 V
18
-
-
ns
74HC_HCT373
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 13 December 2011
© NXP B.V. 2011. All rights reserved.
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