TDA8783HLBE-T Datasheet, PDF (13/28 Pages) NXP Semiconductors – 40 Msps, 10-bit analog-to-digital interface for CCD cameras

Philips Semiconductors
40 Msps, 10-bit analog-to-digital
interface for CCD cameras
Product specification
TDA8783
Table 1 Serial interface programming
ADDRESS BITS
A2
A1
A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
DATA BITS D9 to D0
OFD output control (D7 to D0).
Cut-off frequency of CDS and AGC. Only the 4 LSBs (D3 to D0) are used for
CDS. D4 to D7 are used for AGC. D8 and D9 should be set to logic 0.
AGC gain control (D8 to D0).
Partial standby controls for power consumption optimization. Only the 4 LSBs
(D3 to D0) are used. Edge control for pulses SHP, SHD, CLAMP and
clock ADC:
D0 = 1: CDS + AGC in standby; I_CCA + I_CCD = 35 mA
D1 = 1: OFD DAC in standby; I_CCA + I_CCD = 95 mA
D2 = 1: 6 dB amplifier (output on AMPOUT pin) in standby;
I_CCA + I_CCD = 95.5 mA
D3 = 1: SHP and SHD activated with falling edge (for positive pulse)
D4 = 1: CLPDM, CLPOB and CLPADC activated on HIGH level; note 1
D5 = 0: CLKADC activated with falling edge
D6 must be set to logic 0.
Clamp reference DAC (D9 to D0).
Note
1. When CLPADC is HIGH (D4 = 1: serial interface), the ADC input is clamped to voltage level V_ref.
V_ref is connected to ground via a capacitor.
Table 2 Standby selection
STDBY
1
0
DATA BITS D9 to D0
LOW
active
I_CCA + I_CCD (TYP.)
4 mA
96 mA
2002 Oct 23
13