PIP212-12M Datasheet, PDF (13/21 Pages) NXP Semiconductors – DC-to-DC converter powertrain

NXP Semiconductors
PIP212-12M
DC-to-DC converter powertrain
12.3 DrMOS compatibility
The PIP212-12M can be configured to be compatible with the Intel DrMOS specification.
Conformance to the Intel DrMOS specification requires that an external power supply to
the V_DDG pin is used and hence the internal V_DDG regulator must be disabled by
connecting the VDDG_EN pin to V_SSC. The PRDY flag is not used and should be left
unconnected on the PCB. The external boost capacitor should also be connected
between CBP and V_O and not CBP and CBN with the CBN pin being left unconnected on
the PCB. In addition, V_SSC pin 7 and V_SSO pin 39 to pin 41 should be left unconnected on
the PCB. Note that the sizes of PAD 1, PAD 2 and PAD 3 can vary between different
DrMOS vendors. The PCB footprint must be modified to take the pinning modifications
and pad size differences into account. To ensure footprint compatibility with other DrMOS
products, it is recommended that the latest multiple vendor compatibility PCB footprint
contained within the Intel DrMOS specification is used and that the relevant DrMOS
product data sheet is checked for compatibility.
13. Marking
terminal 1
index area
TYPE No.
DIFFUSION LOT No.
MANUFACTURING CODE
COUNTRY OF ORIGIN
03ao89
TYPE No: PIP212-12M_NN (NN is revision number)
DIFFUSION LOT No: 7 characters
MANUFACTURING CODE; see Figure 15
COUNTRY OF ORIGIN: Korea
Fig 14. SOT684-4 marking
RoHS compliant
G = RoHS indicator
Mask code
N1I = Mask layout version
Diffusion centre
h = Hazel Grove,
UK _hfGYYWWN1I
Assembly centre
f = Amkor Korea
Date code
YY = last two digits of year
WW = week number
03ai72
Fig 15. Interpretation of manufacturing code
PIP212-12M_4
Product data sheet
Rev. 04 — 23 October 2006
© NXP B.V. 2006. All rights reserved.
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