TDA19977A Datasheet, PDF (12/40 Pages) NXP Semiconductors – Triple input HDMI 1.4a compliant receiver interface with equalizer

NXP Semiconductors
TDA19977A; TDA19977B
Triple input HDMI receiver interface with digital processing
8.10 Packet extraction
Information sent during the Data Island periods are extracted from the HDMI data stream.
Audio clock regeneration, general control and Info Frames can be read using the I²C-bus
while audio samples are sent to the audio FIFO.
The TDA19977A; TDA19977B can receive the new HDMI 1.4a packets, general control
and color gamut metadata information packets.
In audio applications, the TDA19977A; TDA19977B manages HBR packets for high bit
rate compressed audio streams (IEC 61937), OBA samples and DST packets for OBA
and SACD with DSD and DST audio streams.
The TDA19977A; TDA19977B includes a two channel status decoder supporting
multi-channel reception for audio sample packets. This enables the user to obtain channel
status information from the IEC 60958/IEC 61937 stream such as:
• The audio stream type (non-linear as IEC 61937 or L-PCM as IEC 60958)
• Copyright protection
• Sampling frequency
Refer to IEC 60958/IEC 61937 specifications for more details.
An update of each Info Frame or the channel status content is indicated by a register bit
and the HIGH-to-LOW transition on output pin VAI. This makes CPU polling unnecessary.
8.11 Audio PLL
The TDA19977A; TDA19977B generates a 128/256/512 × f_s system clock enabling the
use of simple audio DACs without an integrated PLL, such as the UDA1334BTS. The
programming of the audio PLL can be either automatic, using the audio clock
regeneration parameters found in the Data Islands or set manually using the I²C-bus.
All standard audio sampling frequencies 32 kHz, 44.1 kHz, 88.2 kHz, 176.4 kHz, 48 kHz,
96 kHz and 192 kHz are accepted by the device.
8.12 Audio formatter
Audio samples can be output in either S/PDIF, I²S-bus formats or DSD (SACD). In I²S-bus
or S/PDIF modes, up to eight audio channels can be controlled using the audio port pins
(AP0 to AP5). In DSD mode (SACD), up to six audio channels can be controlled using
these pins. The audio port mapping depends on the channel allocation (see Table 4,
Table 5 and Table 6 for detailed information).
TDA19977A_TDA19977B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 19 November 2010
© NXP B.V. 2010. All rights reserved.
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