TDA19977A Datasheet, PDF (1/40 Pages) NXP Semiconductors – Triple input HDMI 1.4a compliant receiver interface with equalizer

TDA19977A; TDA19977B
Triple input HDMI 1.4a compliant receiver interface with
equalizer (up to 1080p for HDTV, and UXGA for PC formats
Rev. 3 — 19 November 2010
Product data sheet
1. General description
The TDA19977A; TDA19977B is a three input HDMI 1.4a compliant receiver with
embedded EDID memory. The built-in auto-adaptive equalizer, improves signal quality
and allows the use of cable lengths of up to 25 m which are laboratory tested with a
0.5 mm (24 AWG) cable at 2.05 gigasamples per second. The HDCP (TDA19977A only)
key set is stored in non-volatile OTP (One Time Programmable) memory for maximum
security. In addition, the TDA19977A; TDA19977B is delivered with software drivers to
ease configuration and use.
The TDA19977A; TDA19977B supports:
• TV resolutions:
– 480i (1440 × 480i at 60 Hz), 576i (1440 × 576i at 50 Hz) to HDTV (up to
1920 × 1080p at 50/60 Hz)
– WUXGA (1920 × 1200p at 60 Hz) reduced blanking format
• PC resolutions:
– VGA (640 × 480p at 60 Hz) to UXGA (1600 × 1200p at 60 Hz)
• Deep Color mode in 10-bit and 12-bit (up to 205 MHz TMDS clock)
• Gamut boundary description
• IEC 60958/IEC 61937, OBA (One Bit Audio), DST (Direct Stream Transfer) and HBR
(High Bit Rate) stream
The TDA19977A; TDA19977B includes:
• An enhanced PC and TV format recognition system
• Generation of a 128/256/512 × f_s system clock allowing the use of simple audio DACs
without an integrated PLL (such as the UDA1334BTS)
• An embedded oscillator (an external crystal can also be used)
• Improved audio clock generation using an external reference clock
• OBA (as used in SACD), DST and HBR stream support
The TDA19977A; TDA19977B converts HDMI streams with or without HDCP
(TDA19977A only) into RGB or YCbCr digital signals. The YCbCr digital output signal can
be 4:4:4 or 4:2:2 semi-planar format based on the ITU-R BT.601 standard or 4:2:2 based
on the ITU-R BT.656 format. The device can adjust the output timing of the video port by
altering the values of t_su(Q) and t_h(Q). In addition, all settings are controllable using the
I²C-bus.