LPC4370 Datasheet, PDF (113/150 Pages) NXP Semiconductors – 32-bit ARM Cortex-M4 + 2 x M0 MCU 282 kB SRAM Ethernet two HS USBs 80 Msps 12-bit ADC configurable peripherals

NXP Semiconductors
LPC4370
32-bit ARM Cortex-M4/M0 microcontroller
11.12 SPIFI
Table 24. Dynamic characteristics: SPIFI
T_amb = 40 C to 85 C; 2.2 V  V_DD(REG)(3V3)  3.6 V; 2.7 V  V_DD(IO)  3.6 V. C_L = 10 pF. Simulated
values.
Symbol
Parameter
Min
Max
Unit
T_cy(clk)
clock cycle time
9.6
t_DS
data set-up time
3.4
t_DH
data hold time

t_v(Q)
data output valid time
-
t_h(Q)
data output hold time
5
-
ns
-
ns
-
ns
8
ns
-
ns
SPIFI_SCK
T_cy(clk)
SPIFI data out
SPIFI data in
t_v(Q)
DATA VALID
DATA VALID
DATA VALID
t_DS
t_DH
DATA VALID
t_h(Q)
Fig 29. SPIFI timing
002aah409
11.13 SGPIO timing
The following considerations apply to SGPIO timing:
• SGPIO input signals are synchronized by the internal clock SGPIO_CLOCK. To
guarantee that no samples are missed, all input signals should have a duration of at
least one SGPIO_CLOCK cycle plus the set-up and hold times.
• When an external clock input is used to generate output data, synchronization causes
a latency of at least one SGPIO_CLOCK cycle. The maximum output data rate is one
output every two SGPIO_CLOCK cycles.
• Synchronization also causes a latency of one SGPIO_CLOCK cycle when sampling
several inputs. This may cause inputs with very similar timings to be sampled with a
difference of one SGPIO_CLOCK cycle.
LPC4370
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 21 October 2013
© NXP B.V. 2013. All rights reserved.
113 of 150