LPC4370 Datasheet, PDF (100/150 Pages) NXP Semiconductors – 32-bit ARM Cortex-M4 + 2 x M0 MCU 282 kB SRAM Ethernet two HS USBs 80 Msps 12-bit ADC configurable peripherals

NXP Semiconductors
LPC4370
32-bit ARM Cortex-M4/M0 microcontroller
Table 12. Peripheral power consumption 12-bit ADCHS
Peripheral
Branch clock
I_DD(REG)(3V3) in mA
Branch clock
Branch clock
frequency = 39 MHz frequency = 78 MHz
ADCHS (12-bit ADC) CLK_ADCHS,
1.1
2.3
CLK_M4_ADCH
ADCHS (12-bit ADC) CLK_ADCHS,
28.5
41.6
CLK_M4_ADCH
Conditions
Peripheral power consumption;
no ADC conversions
Peripheral power consumption;
ADC converting samples at
CLK_ADCHS frequency
10.3 BOD static characteristics
Table 13. BOD static characteristics^[1]
T_amb = 25 C; simulated values for nominal processing.
Symbol Parameter
Conditions
Min
Typ
Max Unit
V_th
threshold voltage interrupt level 0
assertion
-
2.75
-
V
de-assertion
-
2.92
-
V
interrupt level 1
assertion
-
2.85
-
V
de-assertion
-
3.00
-
V
interrupt level 2
assertion
-
2.95
-
V
de-assertion
-
3.12
-
V
interrupt level 3
assertion
-
3.05
-
V
de-assertion
-
3.19
-
V
reset level 0
assertion
-
1.70
-
V
de-assertion
-
1.85
-
V
reset level 1
assertion
-
1.80
-
V
de-assertion
-
1.95
-
V
reset level 2
assertion
-
1.90
-
V
de-assertion
-
2.05
-
V
reset level 3
assertion
-
2.00
-
V
de-assertion
-
2.15
-
V
[1] Interrupt and reset levels are selected by writing to the BODLV1/2 bits in the control register CREGE0, see
the LPC43xx user manual.
LPC4370
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 21 October 2013
© NXP B.V. 2013. All rights reserved.
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