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74HC75N Datasheet, PDF (10/20 Pages) NXP Semiconductors – Quad bistable transparant latch
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Philips Semiconductors
74HC75
Quad bistable transparant latch
Table 8: Dynamic characteristics …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; unless otherwise specified, see Figure 10.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
CPD
power dissipation
VI = GND to VCC
capacitance per latch
[1] -
42
-
pF
Tamb = −40 °C to +85 °C
tPHL, tPLH
propagation delay
nD to nQ
see Figure 6
VCC = 2.0 V
-
-
140
ns
VCC = 4.5 V
-
-
28
ns
VCC = 6.0 V
-
-
24
ns
propagation delay
nD to nQ
see Figure 7
VCC = 2.0 V
-
-
150
ns
VCC = 4.5 V
VCC = 6.0 V
-
-
30
ns
-
-
26
ns
propagation delay
LEnn to nQ
see Figure 9
VCC = 2.0 V
-
-
150
ns
VCC = 4.5 V
-
-
30
ns
VCC = 6.0 V
-
-
26
ns
propagation delay
LEnn to nQ
see Figure 9
VCC = 2.0 V
-
-
155
ns
VCC = 4.5 V
-
-
31
ns
tTHL, tTLH
VCC = 6.0 V
output transition time see Figure 6 and 7
-
-
26
ns
VCC = 2.0 V
-
-
95
ns
VCC = 4.5 V
-
-
19
ns
VCC = 6.0 V
-
-
16
ns
tW
enable pulse width see Figure 9
HIGH
VCC = 2.0 V
100
-
-
ns
VCC = 4.5 V
20
-
-
ns
VCC = 6.0 V
17
-
-
ns
tsu
set-up time nD to
see Figure 8
LEnn
VCC = 2.0 V
75
-
-
ns
VCC = 4.5 V
15
-
-
ns
VCC = 6.0 V
13
-
-
ns
th
hold time nD to LEnn see Figure 8
VCC = 2.0 V
3
-
-
ns
VCC = 4.5 V
3
-
-
ns
VCC = 6.0 V
3
-
-
ns
9397 750 13816
Product data sheet
Rev. 03 — 12 November 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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