74HC75N Datasheet, PDF (1/20 Pages) NXP Semiconductors – Quad bistable transparant latch

74HC75
Quad bistable transparant latch
Rev. 03 — 12 November 2004
Product data sheet
1. General description
The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power
Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC
standard no. 7A.
The 74HC75 has four bistable latches. The two latches are simultaneously controlled by
one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data
enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs
(nD) as long as LEnn is HIGH (transparent). The data on the nD inputs one set-up time
prior to the HIGH-to-LOW transition of the LEnn will be stored in the latches. The latched
outputs remain stable as long as the LEnn is LOW.
2. Features
s Complementary Q and Q outputs
s V_CC and GND on the center pins
s Low-power dissipation
s Complies with JEDEC standard no. 7A
s ESD protection:
x HBM EIA/JESD22-A114-B exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V.
s Multiple package options
s Specified from −40 °C to +80 °C and from −40 °C to +125 °C.