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PSMN3R0-30YL_09 Datasheet, PDF (1/14 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET | |||
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PSMN3R0-30YL
N-channel TrenchMOS logic level FET
Rev. 03 â 28 December 2009
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
industrial and communications applications.
1.2 Features and benefits
 High efficiency due to low switching
and conduction losses
 Suitable for logic level gate drive
sources
1.3 Applications
 Class-D amplifiers
 DC-to-DC converters
 Motor control
 Server power supplies
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter
Conditions
Min Typ Max Unit
VDS
drain-source voltage Tj ⥠25 °C; Tj ⤠175 °C
-
-
30 V
ID
drain current
Tmb = 25 °C; VGS = 10 V;
[1] -
-
100 A
see Figure 1
Ptot
total power
dissipation
Tmb = 25 °C; see Figure 2
-
-
81 W
Dynamic characteristics
QGD
gate-drain charge VGS = 4.5 V; ID = 10 A;
VDS = 12 V; see Figure 14
and 15
-
5.1 -
nC
QG(tot) total gate charge
Static characteristics
VGS = 4.5 V; ID = 10 A;
VDS = 12 V; see Figure 14
-
21 -
nC
RDSon
drain-source
VGS = 10 V; ID = 15 A;
on-state resistance Tj = 25 °C
-
2.19 3
mâ¦
[1] Continuous current is limited by package.
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