74HC259 Datasheet, PDF (1/21 Pages) NXP Semiconductors – 8-bit addressable latch

74HC259; 74HCT259
8-bit addressable latch
Rev. 04 — 25 February 2009
Product data sheet
1. General description
The 74HC259; 74HCT259 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard No. 7-A.
The 74HC259; 74HCT259 are high-speed 8-bit addressable latches designed for general
purpose storage applications in digital systems. They are multifunctional devices capable
of storing single-line data in eight addressable latches and providing a 3-to-8 decoder and
multiplexer function with active HIGH outputs (Q0 to Q7). They also incorporates an active
LOW common reset (MR) for resetting all latches as well as an active LOW enable input
(LE).
The 74HC259; 74HCT259 has four modes of operation:
• Addressable latch mode, in this mode data on the data line (D) is written into the
addressed latch. The addressed latch will follow the data input with all non-addressed
latches remaining in their previous states.
• Memory mode, in this mode all latches remain in their previous states and are
unaffected by the data or address inputs.
• Demultiplexing mode (or 3-to-8 decoding), in this mode the addressed output follows
the state of the data input (D) with all other outputs in the LOW state.
• Reset mode, in this mode all outputs are LOW and unaffected by the address inputs
(A0 to A2) and data input (D).
When operating the 74HC259; 74HCT259 as an address latch, changing more than one
address bit could impose a transient wrong address. Therefore, this should only be done
while in the Memory mode.
2. Features
I Combined demultiplexer and 8-bit latch
I Serial-to-parallel capability
I Output from each storage bit available
I Random (addressable) data entry
I Easily expandable
I Common reset input
I Useful as a 3-to-8 active HIGH decoder
I Input levels:
N For 74HC259: CMOS level
N For 74HCT259: TTL level