NAND08GAH0A Datasheet, PDF (78/116 Pages) Numonyx B.V – 1 Gbyte, 2 Gbyte, 1.8 V/3 V supply, NAND Flash memories with MultiMediaCard™ interface

Timings
NAND08GAH0A, NAND16GAH0D
9.2
Data Read timings
9.2.1
Single Block Read
The host selects one device for data read operation by issuing a CMD7 command. It then
sends a CMD16 command to set the valid block length for block oriented data transfer.
Figure 19 shows the timing diagram for a Single Block Read operation. The sequence starts
with a single block read command (CMD17) which specifies the start address in the
argument field. The response is sent on the CMD line as usual. Data transmission starts
N_AC clock cycles after the end bit of the host command. After the last data bit, the CRC
check bits are suffixed to allow the host to check for transmission errors.
Figure 19. Single Block Read command timing diagram
Host Command
N_CR
Cycles
Card Response
CMD _{S T} Content _CRC E _{Z Z P * * *} P S _T Content _{CRC E}
N_AC Cycles
Read Data
DAT Z Z Z _{* * * * Z} Z Z Z Z Z P _{* * * * * * * * * P S D D} D _{* * *}
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9.2.2
Multiple Block Read
In Multiple Block Read mode, the device sends a continuous flow of data blocks following
the initial host read command. The data flow is terminated by a STOP_TRANSMISSION
command (CMD12).
Figure 20 describes the timing of the data blocks and Figure 21 the response to a
STOP_TRANSMISSION command. The data transmission stops two clock cycles after the
end bit of the STOP_TRANSMISSION command.
Figure 20. Multiple Block Read command timing diagram
Host Command
N_CR
Cycles
Card Response
CMD S T Content CRC E Z Z P _* P S T Content CRC E Z Z P P P P P P P P P P P P P
N_AC Cycles
Read Data
N_AC Cycles Read Data
DAT Z _{Z Z * * * * Z} Z Z Z Z Z _{P * * * * * * * * P S D D} D _{* * * * D E P * * * * * * P} S _{D D D D} D
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