NAND08GAH0A Datasheet, PDF (109/116 Pages) Numonyx B.V – 1 Gbyte, 2 Gbyte, 1.8 V/3 V supply, NAND Flash memories with MultiMediaCard™ interface

NAND08GAH0A, NAND16GAH0D
Serial peripheral interface (SPI) mode
Figure 47. CSD and CID register Read timing diagram
CS
DataIn
DataOut
HL LL
N_CS
X H**H
Z ZHHHH
*********************
L L L HHHH
N_EC
Read Command H H H H H
**********
H*H XX X X
N_CR
N_CX
******
H * * H Card Response H * * H Data Block H H H H Z Z Z
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1. The timeout between the device response and the data block is N_CX as N_AC is not known yet.
10.9.3 Data Write timings
The host may deselect a device at any moment during single and Multiple Block Write
operations. The device will release the DataOut line one clock cycle after it is deselected
(CS High). To check whether the device is still busy, the host must reselect it by reasserting
CS Low. The device will then take control of the DataOut line one clock cycle after being
reselected.
In Multiple Block Write operations, the timings from the command being issued to the first
data block being transmitted by the device are the same as for single block Write operations
(see Figure 48 and Figure 49 for details). The timing of STOP TRANSMISSION prefixes is
the same as that of data blocks. After the Stop tran is received by the device, the data on the
DataOut line is undefined for one byte (N_BR), then a Busy message may be sent by the
device.
Refer to Table 71 for timing values.
Figure 48. Single Block Write timing diagram
CS
DataIn
DataOut
HL
*****************
L L L L L L L L LHHH L L L L
N_CS
N_WR
N_EC N_DS
X H * H Write Command H H H H ^H H H H * H ^{Data Block} H H H H H * H X * X H H H H
N_CR
Z ZHHH
****
H * H ^{Card Resp} H H H H H H H Data Resp Busy L Z Z Z Busy H
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Figure 49. Multiple Block Write timing diagram
CS
DataIn
DataOut
L
************
L L L LL L L LLLL LLLL LLL L L
N_WR
N_WR
H Data Block H H H H H H H H * H Data Block H H H H H H H H * H StopTran H H H H H
N_BR
H H H H H Data Resp Busy H H H H H H H Data Resp Busy H H H H H H X * X Busy
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