28F640W30 Datasheet, PDF (63/102 Pages) Intel Corporation – 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30)

Numonyx™ Wireless Flash Memory (W30)
11.3.5
The host programmer must reset its initial verify-word address to the same starting
location supplied during the program phase. It then reissues each data word in the
same order as during the program phase. Like programming, the host can write each
subsequent data word to WA₀ or it can increment through the block addresses.
The verification phase concludes when the interfacing programmer writes to a different
block address. The data supplied must be FFFFh. Upon completion of the verify phase,
the flash device enters the EFP exit phase.
Exit
SR[7]=1 indicates that the flash device has returned to normal operating conditions.
Perform a full status check at this time, to verify that the entire block programmed
successfully. After EFP exit, any valid CUI command can be issued.
November 2007
Order Number: 290702-13
Datasheet
63