28F640W30 Datasheet, PDF (61/102 Pages) Intel Corporation – 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30)

Numonyx™ Wireless Flash Memory (W30)
11.3
11.3.1
Figure 37, “Examples of VPP Power Supply Configurations” on page 78 shows examples
of flash device power supply usage in various configurations.
The 12-V V_PP mode enhances programming performance during the short time period
typically found in manufacturing processes. However, this mode is not intended for
extended use.12 V can be applied to V_PP during program and erase operations as
specified in Section 5.2, “Operating Conditions” on page 24. VPP can be connected to
12 V for a total of t_PPH hours maximum. Stressing the flash device beyond these limits
might cause permanent damage.
Enhanced Factory Program (EFP)
EFP substantially improves flash device programming performance through a number
of enhancements to the conventional 12-Volt word program algorithm. The more
efficient WSM algorithm in EFP eliminates the traditional overhead delays of the
conventional word program mode in both the host programming system and the flash
device. Changes to the conventional word programming flowchart and internal WSM
routine were developed because of today's beat-rate-sensitive manufacturing
environments; a balance between programming speed and cycling performance was
attained.
The host programmer writes data to the flash device and checks the Status Register to
determine when the data has completed programming. This modification cuts write bus
cycles approximately in half.
• Following each internal program pulse, the WSM increments the flash device
address to the next physical location.
• Programming equipment can then sequentially stream program data throughout an
entire block without having to setup and present each new address.
In combination, these enhancements reduce much of the host programmer overhead,
enabling more of a data streaming approach to flash device programming.
EFP further speeds up programming by performing internal code verification. With this
feature, PROM programmers can rely on the flash device to verify that it has been
programmed properly. From the flash device side, EFP streamlines internal overhead by
eliminating the delays previously associated with switching voltages between
programming and verify levels at each memory-word location.
EFP consists of four phases: setup, program, verify, and exit. Refer to Figure 29,
“Enhanced Factory Program Flowchart” on page 64 for a detailed graphical
representation of how to implement EFP.
EFP Requirements and Considerations
Table 24: EFP Requirements and Considerations
EFP Requirements
EFP Considerations
Ambient temperature: T_A = 25 °C ±5 °C
V_CC within specified operating range
V_PP within specified V_PPH range
Target block unlocked
Block cycling below 100 erase cycles ¹
RWW not supported²
EFP programs one block at a time
EFP cannot be suspended
1.
Recommended for optimum performance. Some degradation in performance might occur if this limit is exceeded, but the
internal algorithm will continue to work properly.
2.
Code or data cannot be read from another partition during EFP.
November 2007
Order Number: 290702-13
Datasheet
61