28F800C3 Datasheet, PDF (59/70 Pages) Intel Corporation – Advanced+ Boot Block Flash Memory (C3)

C3 Discrete
Figure 20: Block Erase Flowchart
BLOCK ERASE PROCEDURE
Start
Write 0x20,
Block Address
(Block Erase)
Write 0xD0,
Block Address ^{(Erase Confirm)}
Read Status
Register
SR[7] =
0
1
Full Erase
Status Check
(if desired)
No
Suspend
Erase
Suspend
Erase
Loop
Yes
Bus
Operation
Command
Comments
Write
Block
Erase
Setup
Data = 0x20
Addr = Block to be erased (BA)
Write
Erase Data = 0xD0
Confirm Addr = Block to be erased (BA)
Read
None
Status Register data. Toggle CE# or
OE# to update Status register data
Check SR[7]:
Idle
None 1 = WSM ready
0 = WSM busy
Repeat for subsequent block erasures.
Full Status register check can be done after each block erase
or after a sequence of block erasures.
Write 0xFF after the last operation to enter read array mode.
Block Erase
Complete
FULL ERASE STATUS CHECK PROCEDURE
Read Status
Register
SR[3] = ¹
0
SR[4,5] = ^1,1
0
SR[5] = ¹
0
SR[1] = ¹
0
Block Erase
Successful
V_PP Range
Error
Command
Sequence Error
Block Erase
Error
Block Locked
Error
Bus
Operation
Command
Comments
Idle
None
Check SR[3]:
1 = V_PP Range Error
Idle
None
Check SR[4,5]:
Both 1 = Command Sequence Error
Idle
None
Check SR[5]:
1 = Block Erase Error
Check SR[1]:
Idle
None 1 = Attempted erase of locked block;
erase aborted.
SR[1,3] must be cleared before the Write State Machine will
allow further erase attempts.
Only the Clear Status Register command clears SR[1, 3, 4, 5].
If an error is detected, clear the Status register before
attempting an erase retry or other error recovery.
March 2008
290645-24
Datasheet
59