28F800C3 Datasheet, PDF (28/70 Pages) Intel Corporation – Advanced+ Boot Block Flash Memory (C3)

C3 Discrete
Table 11: Read Operations—32-Mbit Density
Densit
y
32 Mbit
Produc
t
70 ns
90 ns
100 ns
110 ns
#
Sym
Paramet
er
V_CC
2.7 V–3.6
V
2.7 V–3.6
V
3.0 V–3.3
V
2.7 V–3.3
V
3.0 V–3.3
V
2.7 V–3.3
V
Note
s
Min Max Min Max Min Max
(ns) (ns) (ns) (ns) (ns) (ns)
Min
(ns)
Max
(ns)
Min
(ns
)
Max
(ns
)
Min Max
(ns) (ns)
R1 t_AVAV Read Cycle Time
R2
t_AVQV
Address to Output
Delay
70
90
90
100
100
110
70
90
90
100
100
110
R3 t_ELQV CE# to Output Delay
70
90
90
100
100
110
R4 t_GLQV OE# to Output Delay
20
20
30
30
30
30
R5 t_PHQV RP# to Output Delay
150
150
150
150
150
150
R6
t_ELQX
CE# to Output in
Low Z
0
0
0
0
0
0
R7
t_GLQX
OE# to Output in
Low Z
0
0
0
0
0
0
R8
t_EHQZ
CE# to Output in
High Z
20
20
20
20
20
20
R9
t_GHQZ
OE# to Output in
High Z
20
20
20
20
20
20
Output Hold from
Address, CE#, or
R10 t_OH OE# Change,
0
0
0
0
0
0
Whichever Occurs
First
Notes:
1.
OE# may be delayed up to t_ELQV–t_GLQV after the falling edge of CE# without impact on t_ELQV.
2.
Sampled, but not 100% tested.
3.
See Figure 9, “Read Operation Waveform” on page 29.
4.
See Figure 11, “AC Input/Output Reference Waveform” on page 34 for timing measurements
and maximum allowable input slew rate.
3,4
3,4
1,3,4
1,3,4
3,4
2,3,4
2,3,4
2,3,4
2,3,4
2,3,4
Datasheet
28
March 2008
290645-24