M58WR016KU Datasheet, PDF (119/123 Pages) STMicroelectronics – 16- or 32-Mbit (×16, Mux I/O, Multiple Bank, Burst) 1.8 V supply Flash memories

M58WRxxxKU, M58WRxxxKL
Command interface state tables
Table 48.
Command interface states - Modify table, next output⁽¹⁾
Command Input⁽²⁾
Current CI State
Read
Array⁽³⁾
DWP, QWP
Setup⁽⁴⁾⁽⁵⁾
Block
Erase
Setup⁽⁴⁾⁽⁵⁾
(FFh) (35h, 56h) _(20h)
EFP
Setup
(30h)
Quad-
EFP
Setup
(75h)
Erase Confirm
P/E Resume,
Block Unlock
confirm, EFP
Confirm (D0h)
Program/
Erase
Suspend
(B0h)
Read
Status
Register
(70h)
Clear Status ^{Read Electronic}
Register^{(6) signature, Read}
CFI Query (90h,
(50h)
98h)
Program Setup
Erase Setup
OTP Setup
Program Setup in
Erase Suspend
EFP Setup
EFP Busy
Status Register
EFP Verify
Quad EFP Setup
Quad EFP Busy
Lock/CR Setup
Lock/CR Setup in
Erase Suspend
OTP Busy
Status Register
Ready
Program Busy
Erase Busy
Program/Erase
Suspend
Array
Status Register
Output Unchanged
Status
Output
Register Unchanged
Electronic
Signature/CFI
Program Busy in
Erase Suspend
Program Suspend
in Erase Suspend
Illegal State
Output Unchanged
1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple
Enhanced Factory Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase
Controller, IS = Illegal State, ES = Erase suspend, PS = Program suspend.
2. The output state shows the type of data that appears at the outputs if the bank address is the same as the command
address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI Query mode,
depending on the command issued. Each bank remains in its last output state until a new command is issued. The next
state does not depend on the bank’s output state.
3. At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined
data output.
4. The two cycle command should be issued to the same bank address.
5. If the P/E.C. is active, both cycles are ignored.
6. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended.
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