NTE2114 Datasheet, PDF (3/4 Pages) NTE Electronics – Integrated Circuit MOS, Static 4K RAM, 300ns

Truth Table:
CS
WE
I/O
MODE
H
X
Hi–Z
Not Selected
L
L
H
Write 1
L
L
L
Write 0
L
H
D_OUT
Read
Functional Description:
Two pins control the operation of the NTE2114. Chip Select (CS) enables write and read operations
and controls TRI–STATING of the data–output buffer. Write Enable (WE) chooses between READ
and WRITE modes and also controls output TRI–STATING. The truth table details the states pro-
duced by combinations of the CS and WE controls.
During READ–cycle timing, WE is kept high. Independent of CS, any change in address code causes
new data to be fetched and brought to the output buffer. CS must be low, however, for the output buffer
to be enabled and transfer the data to the output pin.
Address access time, t_A, is the time required for an address change to produce new data at the output
pin, assuming CS has enabled the output buffer prior to data arrival. Chip Select–to–output delay,
t_CO, is the time required for CS to enable the output buffer and transfer previously fetched data to the
output–pin. Operation with CS continuously held low is permissible.
Writing occurs only during the time both CS and WE are low. Minimum write pulse width, t_WP, refers
to this simultaneous low region. Data set–up and hold times are measured with respect to whichever
control first rises. Successive write operations may be performed with CS continuously held low. WE
then is used to terminate WRITE between address changes. Alternatively, WE may be held low for
successive WRITES and CS used for WRITE interruption between address change.
In any event, either WE or CS (or both) must be high during address transitions to prevent erroneous
WRITE.
Pin Connection Diagram
A6 1
A5 2
A4 3
A3 4
A0 5
A1 6
A2 7
CS 8
GND 9
18 V_CC
17 A7
16 A8
15 A9
14 I/O 1
13 I/O 2
12 I/O 3
11 I/O 4
10 WE