PC87373 Datasheet, PDF (98/174 Pages) National Semiconductor (TI) – LPC SuperI/O with Glue Functions

6.0 System Wake-Up Control (SWC) (Continued)
6.4.2 General-Purpose Status 1 Register (GPE1_STS)
This register contains the global Power Management Event status bit. This register belongs to the General-Purpose Event
1 register group of the ACPI generic-feature space registers.
The status bit behaves according to the Sticky Status Bit definition in the ACPI Specification (i.e., the bit is set when the level
of the hardware signal is high and is only cleared by the software writing 1 to it).
Power Well: V_SB3
Location: Offset 00h
Type:
R/W1C
Bit
Name
Reset
7
6
5
4
3
2
1
0
Reserved
PME_STS
0
0
0
0
0
0
0
0
Bit
Description
7-1 Reserved.
0 PME_STS (Power Management Event Status). Indicates that an enabled Power Management event has
occurred. This bit is set if at least one enabled event (in GPE1_EN_0 to GPE1_EN_3 registers) is active (in
GPE1_STS_0 to GPE1_STS_3 registers). This bit can be reset by writing 1 only if all the enabled events are
inactive.
0: Inactive (default)
1: At least one enabled “child” event was active since this bit was last cleared
6.4.3 General-Purpose Enable 1 Register (GPE1_EN)
This register contains the global Power Management Event enable bit. This register belongs to the General-Purpose Event
1 register group of the ACPI generic-feature space registers. It is reset to 00h.
The enable bit behaves according to the Enable Bit definition in the ACPI Specification (i.e., the bit can be read or written
by software).
Power Well: V_SB3
Location: Offset 04h
Type:
R/W
Bit
Name
Reset
7
6
5
4
3
2
1
0
Reserved
PME_EN
0
0
0
0
0
0
0
0
Bit
Description
7-1 Reserved.
0 PME_EN (Power Management Event Enable). Controls SCI (SIOPME) generation by a set PME_STS bit. If
this bit is set, a set PME_STS bit in GPE1_STS register generates an SCI interrupt.
0: Disable SCI (default)
1: Enable SCI generation by a set PME_STS bit
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