PC87373 Datasheet, PDF (109/174 Pages) National Semiconductor (TI) – LPC SuperI/O with Glue Functions

7.0 Fan Speed Control (Continued)
7.3.3 Fan Speed Control Duty-Cycle Register (FCDCR)
This register controls the duty-cycle of the FANPWM signal. It is reset by hardware to FFh.
Power Well: V_DD3
Location: Device specific
Type:
R/W
Bit
Name
Reset
7
6
5
4
3
2
1
0
DUTY-CYC
1
1
1
1
1
1
1
1
Bit
Description
7-0 DUTY-CYC (Duty-Cycle Value). The binary value of this 8-bit field determines the number of clock cycles (out
of a 256-cycle period) during which the PWM output is high (a high FANPWM is either equal to or the inverse
of the PWM output, depending on the FANCTL_INV configuration bit).
00h:
The PWM output is continuously low
01h - FEh: The PWM output is high for [DUTY-CYC] number of clock cycles and low for [256-DUTY-CYC]
number of clock cycles
FFh:
The PWM output is continuously high (default)
7.4 FAN SPEED CONTROL REGISTER BITMAP
Table 41. Fans Speed Control Register Bitmap
Register
Bits
Offset
Mnemonic
7
6
5
4
3
2
1
0
Device Specific^{1 FCPSR CLK_SEL}
PRE-SCALE
Device Specific^{1 FCDCR}
DUTY-CYC
1. The location of this register is defined in Section 3.15.1 on page 67.
Revision 1.1
109
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