PC87373 Datasheet, PDF (161/174 Pages) National Semiconductor (TI) – LPC SuperI/O with Glue Functions

13.0 Device Characteristics (Continued)
13.4.3 Clock Timing
High-Frequency Clock Timing
Symbol Figure Clock Input Parameters
Reference
Conditions
CLOCKI14
Min
Typ
Max
Units
t_CH
t_CL
t_CP
F_CK
t_CR
t_CF
t_14MW
t_14MVAL
51 _{Clock High Pulse Width}¹
29.5
ns
51 _{Clock Low Pulse Width}¹
29.5
ns
51 _{Clock Period}¹ _(50%-50%)
69.14
69.84
70.54
ns
− Clock Frequency
F_CKTYP − 1% 14.31818 F_CKTYP + 1% MHz
51 _{Clock Rise Time}¹ _(20%-80%)
5²
ns
51 _{Clock Fall Time}¹ _(80%-20%)
5²
ns
52 Clock Wake-Up Time
V_DD3 stable to clock
start toggling
System dependent
52 _{Clock Valid Time}¹
Clock start toggling
to clock valid
System dependent
1. Not tested. Guaranteed by design.
2. Recommended value
Sym. Fig. Internal Clock Parameter
Reference
Conditions
t_CP 51 _{Clock Period}¹ _(50%-50%)
F_CK − Clock Frequency
t_48MD 52 _{Clock Wake-Up Time}¹
After Clock
Generator enabled
1. Not tested. Guaranteed by characterization.
INT48M
Min
Typ
Max
20.83
48
500
Units
ns
MHz
µs
t_CH
t_CP
V_IH
V_IH
V_IH
V_IL
V_IL
V_IL
t_CL
t_CF
t_CR
Figure 51. High-Frequency Clock Waveform Timing
V_DD3 (Power) ^VDD3ONmin
t_14MW
t_14MVAL
t_CP (CLOCKI14)
CLOCKI14
(14.31818 MHz)
Enable Clock Generator
(Internal)
CKVALID bit
(Internal)
48 MHz Domain
(Internal)
t_48MD
t_CP (48 MHz)
Figure 52. CLOCKI14 and Internal 48 MHz Domain Timing
Revision 1.1
161
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