CR16MCT9 Datasheet, PDF (97/153 Pages) National Semiconductor (TI) – CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller

Buffer 0
BUFFER_ID
CR16CAN
HIDDEN
RECEIVE
BUFFER
Buffer 13
BUFFER_ID
Buffer 14
BUFFER_ID
Figure 60. Receive Buffer Structure
The received data frame will be stored in the first matching
receive buffer beginning with buffer 0. For example, if the
message is accepted by buffer 5, then at the time the mes-
sage will be copied, the RX request is cleared and CR16CAN
will not try to match the frame to any subsequent buffer.
All contents of the hidden receive buffer are always copied
into the respective receive buffer. This includes the received
message ID as well as the received Data Length Code
(DLC); therefore when some mask bits are set to don’t care,
the ID field will get the received message ID which could be
different from the previous ID. The DLC of the receiving buffer
will be updated by the DLC of the received frame. Note that
the DLC of the received message is not compared with the
DLC already present in the CNSTAT register of the message
buffer. This implies that the DLC code of the CNSTAT register
indicates how may data bytes actually belong to the latest re-
ceived message.
The remote frames are handled by the CR16CAN interface
in two different ways. Firstly, remote frames can be received
like data frames by configuring the buffer to be RX_READY
and setting the ID bits including the RTR bit. In that case the
same procedure applies as described for Data Frames. Sec-
ondly, a remote frame can trigger one or more message buff-
er to transmit a data frame upon reception. This procedure is
described under To answer Remote Frames on page 99.
20.5.1 Receive Timing
As soon as CR16CAN receives a dominant bit on the CAN
bus, the receive process is started. The received ID and data
will be stored in the hidden receive buffer if the global or basic
acceptance filtering matches. After the reception of the data,
CR16CAN tries to match the buffer ID of buffer 0...14. The
data will be copied into the buffer after the reception of the 6th
EOF bit as a message is valid at this time. The copy process
of every frame, regardless of the length, takes at least 17 CKI
cycles (see also CPU Access to CR16CAN Registers/Mem-
ory on page 103). Figure 61 illustrates the receive timing.
ARBITRATION FIELD _{DATA FIELD}
SOF ^{+ CONTROL}
(IF PRESENT)
BUS IDLE 1 BIT 12/29 BIT + 6 BIT
n * 8 BIT
CRC
FIELD
16 BIT
ACK
FIELD EOF
2 BIT 7 BIT
IFS
3 BIT
rx_start
BUSY
copy to buffer
Figure 61. Receive Timing
In order to indicate that a frame is waiting in the hidden buffer,
the BUSY bit ST[0] of the selected buffer is set during the
copy procedure. The BUSY bit will be cleared by CR16CAN
right after the data bytes are copied into the buffer. After the
copy process is finished, CR16CAN changes the status field
to RX_FULL. In turn the CPU should change the status field
to RX_READY when the data is processed. When a new ob-
ject has been received by the same buffer, before the CPU
changed the status to RX_READY, the CR16CAN will change
the status to RX_OVERRUN to indicate that at least one
frame has been overwritten by a new one. Table 21 summa-
rizes the current status and the resulting update from the
CR16CAN.
Table 21 Writing to Buffer Status Code During
RX_BUSY
Current Status
RX_READY
RX_NOT_ACTIVE
RX_FULL
Resulting Status
RX_FULL
RX_NOT_ACTIVE
RX_OVERRUN
97
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