CR16MCT9 Datasheet, PDF (18/153 Pages) National Semiconductor (TI) – CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller

8.0 Bus Interface Unit
The Bus Interface Unit (BIU) controls the interface between
the internal core bus and those on-chip modules which are
mapped into BIU zones. These on-chip modules are the flash
EEPROM program memory, the ISP-memory and the I/O-
zone. It determines the configured parameters for bus ac-
cess (such as the number of wait states for memory access)
and issues the appropriate bus signals for the requested ac-
cess.
Note: The device is manufactured in a 224-pin version which
is used in emulation equipment. In the 224-pin device, the
BIU controls access to both on-chip and off-chip memory and
peripherals. Operation of the 224-pin device and the use of
chip-external memory is beyond the scope of this data sheet.
8.1 BUS CYCLES
There are four types of data transfer bus cycles:
— Normal read
— Fast read
— Early write
— Late write
The type of data cycle used in a particular transaction de-
pends on the type of CPU operation (a write or a read), the
type of memory or I/O being accessed, and the access type
programmed into the BIU control registers (early/late write or
normal/fast read).
For read operations, a basic normal read takes two clock cy-
cles, whereas a fast read bus cycle takes one clock cycle.
Upon reset of the device, normal read bus cycles are enabled
by default.
For write operations, a basic late write bus cycle takes two
clock cycles, whereas a basic early write bus cycle takes
three clock cycles. Upon reset of the device, early write bus
cycles are enabled by default. However, late write bus cycles
are needed for ordinary write operations, so this configura-
tion should be changed by the application software (see
Section 8.2.1).
In certain cases, one or more additional clock cycles are add-
ed to a bus access cycle. There are two types of additional
clock cycles for ordinary memory accesses, called internal
wait cycles (TIW) and hold (Thold) cycles.
A wait cycle is inserted in a bus cycle just after the memory
address has been placed on the address bus. This gives the
accessed memory more time to respond to the transaction
request. A hold cycle is inserted at the end of a bus cycle.
This holds the data on the data bus for an extended number
of clock cycles.
8.2 BIU CONTROL REGISTERS
The BIU has a set of control registers that determine how
many wait cycles and hold cycles are to be used for access-
ing memory. Upon start-up of the device, these registers
should be programmed with appropriate values so that the
minimum allowable number of cycles is used. This number
varies with the clock frequency used.
There are four applicable BIU registers: the BIU Configura-
tion (BCFG) register, the I/O Configuration (IOCFG) register,
the Static Zone 0 Configuration (SZCFG0) register and the
Static Zone 1Configuration (SZCFG1) register. These regis-
ters control the bus cycle configuration used for accessing
the various on-chip memory types.
Note: A system configuration register called the Module
Configuration (MCFG) register controls the number of wait
cycles used for accessing the EEPROM data memory. This
register is described in Section 5.1.
8.2.1 BIU Configuration (BCFG) Register
The BIU Configuration (BCFG) Register is a byte-wide, read/
write register that selects either early write or late write bus
cycles. The register address is F900 hex. Upon reset, the
register is initialized to 07 hex. The register format is shown
below.
76543
Reserved
2
Note 1
1
Note 1
0
EWR
EWR
Early Write. This bit is cleared to 0 for late write
operation (two clock cycles to write) or set to 1
for early write operation.
Note 1: These bits (bit 1 or bit 2) control the configuration of
the 224-pin device used in emulation equipment. The CPU
should set this bit to 1 when it writes to the register.
Upon reset, the BCFG register is initialized to 07 hex, which
selects early write operation. However, late write operation is
required for normal device operation, so the software should
change the register value to 06 hex.
8.2.2 I/O Zone Configuration (IOCFG) Register
The I/O Zone Configuration (IOCFG) register is a word-wide,
read/write register that sets the timing and bus characteris-
tics of I/O Zone memory accesses. In the device implemen-
tation, the registers associated to Port B and Port C reside in
the I/O memory array. (These ports are used as a 16-bit data
port, if the device operates in development mode.)
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