CR16MCT9 Datasheet, PDF (103/153 Pages) National Semiconductor (TI) – CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller

The highest priority interrupt source is translated into the bits
IRQ and IST[3:0] as shown in Table 24.
Table 24 Highest Priority Interrupt Code (ICEN=FFFF)
CAN interrupt
request
no request
Error interrupt
Buffer 0
Buffer 1
Buffer 2
Buffer 3
Buffer 4
Buffer 5
Buffer 6
Buffer 7
Buffer 8
Buffer 9
Buffer 10
Buffer 11
Buffer 12
Buffer 13
Buffer 14
IRQ
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IST3
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
IST2
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
IST1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
IST0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
20.7.2 Usage Hints
The interrupt code IST[3:0] can be used within the interrupt
handler as a displacement in order to jump to the relevant
subroutine.
The CAN Interrupt Code Enable (CICEN) register is used in
the CAN interrupt handler if the user wants to service all re-
ceive buffer interrupts first followed by all transmit buffer in-
terrupts. In this case, the user can first enable only all receive
buffer interrupts to be coded, scan and service all pending in-
terrupt requests in the order of their priority. Then, the user
changes the CICEN register to disable all receive buffers, but
enable all transmit buffers and service all pending transmit
buffer interrupt requests according to their priorities.
20.8 TIME STAMP COUNTER
CR16CAN features a free running 16-bit timer (CTMR) incre-
menting every bit time recognized on the CAN bus. The val-
ue of this timer during the ACK slot is captured into the TSTP
register of a message buffer after a successful transmission
or reception of a message. Figure 68 shows a simplified
block diagram of the Time Stamp counter.
16-bit counter
+1
Reset
CAN bits on the bus
ACK slot & buffer 0 active
ACK slot
TSTP register
Figure 68. Time Stamp Counter
The timer can be synchronized over the CAN network by re-
ceiving or transmitting a message to/from buffer 0. In that
case the TSTP register of buffer 0 captures the current
CTMR value during the ACK slot of a message (as above)
and afterwards the CTMR is reset to 0000₂. Synchronization
can be enabled or disabled via the CGCR.TSTPEN bit.
20.9 MEMORY ORGANIZATION
CR16CAN occupies 144 words in the memory address
space. This space is separated into 15*8 + 8(reserved)
words for the message buffers and 14 + 2(reserved) words
for control and status.
20.9.1 CPU Access to CR16CAN Registers/Memory
All memory locations occupied by the message buffers are
shared by the CPU and CR16CAN (dual ported RAM). The
CR16CAN and the CPU normally have single cycle access
to this memory. However, if an access contention occurs, the
access to the memory is altered every cycle until the conten-
tion is resolved. This internal access arbitration is transpar-
ent to the user.
Both word and byte access to the buffer RAM are allowed. If
a buffer is busy during the reception of an object (copy pro-
cess from the hidden receive buffer) or is scheduled for trans-
mission, the CPU has no write access to the data contents of
the buffer. Write to the status/control byte and read access to
the whole buffer is always enabled.
All configuration and status registers can either be accessed
by CR16CAN or the CPU only. These registers provide single
cycle word and byte access without any potential wait state.
All register descriptions within the next sections utilize the fol-
lowing layout:
bit 15
... bit number ...
bit 0
... bit name ...
... reset value ...
... CPU access ...
r = register bit is read only
w = register bit is write only
r/w = register bit is read/write
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