DP8344B Datasheet, PDF (95/184 Pages) National Semiconductor (TI) – Biphase Communications ProcessorㅡBCP

5 0 Device Specifications (Continued)
Signal
In Out
Pin
Reset
State
Description
5 1 3 DATA MEMORY INTERFACE (Continued)
Timing Control
ALE
Out
28
0
Address Latch Enable Demultiplexes AD bus Address should be latched on the
falling edge
READ
Out
29
1
Data memory READ strobe Data is latched on the rising edge
WRITE
Out
30
1
Data memory WRITE strobe Data is presented on the rising edge
5 1 4 TRANSCEIVER INTERFACE
DATA-IN
In
39
X
Logic level serial DATA INput
aALG-IN
In
42
X
Non-inverting AnaLoG INput for biphase serial data
bALG-IN
In
41
X
Inverting AnaLoG INput for biphase serial data
DATA-OUT
Out
38
1
Biphase serial DATA OUTput (inverted)
DATA-DLY
Out
37
1
Biphase serial DATA output DeLaYed by one-quarter bit time
TX-ACT
Out
36
0
Transmitter ACTive Normally low goes high to indicate serial data is being
transmitted Used to enable external line drive circuitry
5 1 5 REMOTE INTERFACE
RAE
In
46
X
Remote Access Enable A ‘‘chip-select’’ input to allow host access of BCP
functions and memory
CMD
In
45
X
CoMmanD input When high remote accesses are directed to the Remote
Interface Configuration register RIC When low remote accesses are directed
to data-memory instruction-memory or program counter as determined by
RIC
REM-RD
In
47
X
REMote ReaD When active along with RAE a remote read cycle is requested
serviced by the BCP when the data bus becomes available
REM-WR
In
48
X
REMote WRite When active along with RAE a remote write cycle is requested
serviced by the BCP when the data bus becomes available
XACK
Out
50
1
Transfer ACKnowledge Normally high goes low on REM-RD or REM-WR going
low (if RAE low) returning high when the transfer is complete Normally used as
a ‘‘wait’’ signal to a remote processor
WR-PEND
Out
49
1
WRite PENDing In a system configuration where remote write cycles are
latched indicates when the latches contain valid data which is yet to be serviced
by the BCP
LOCK
In
44
X
The remote processor uses this input to LOCK out local (BCP) accesses to data-
memory Once the remote processor has been granted the bus LOCK gives it
sole access to the bus and BCP accesses are ‘‘waited’’
LCL
Out
31
0
LoCaL Normally low goes high when the BCP relinquishes the data and
address bus to service a Remote Access
5 1 6 EXTERNAL INTERRUPTS
BIRQ
In Out 53
In
Bi-directional Interrupt ReQuest As an input can be used as an active low
interrupt input (maskable and level-sensitive) As an output can be used to
generate remote system interrupts reset via RIC
NMI
In
52
X
Non-Maskable Interrupt Negative edge sensitive interrupt input
95