DP8344B Datasheet, PDF (106/184 Pages) National Semiconductor (TI) – Biphase Communications ProcessorㅡBCP

5 0 Device Specifications (Continued)
TABLE 5-10 Control Pin Timing (Note 1)
Symbol
ID
Parameter
Formula
Min Max Units
t_W-RST
t_PD-RST-ICLK
t_SU-ALE-WT
t_H-WT-ALE
1 RESET Low
2 RESET Rising to ICLK Rising
3 WAIT Low after ALE High to Extend Cycle
4 WAIT Rising after ALE Falling (Note 2)
t_PD-WT-RDWR 5 WAIT Rising to READ or WRITE Rising
t_SU-RRW-RST
6 REM-RD REM-WR Low to RESET
Rising for BCP to Start
5Ta
4Ta
(MAX(n_DW n_IWb1)a1)Ta
(MAX(n_DW n_IWb1)a1)Ta
TaT_La
2TaT_La
0
ns
0
ns
b21 ns
0
ns
b28 ns
b22
ns
2
ns
15
ns
t_H-RST-RRW
7 REM-RD REM-WR Low after RESET
Rising for BCP to Start
5
ns
t_SU-LK-ICLK
t_PD-LK-ALE
8 LOCK Low before ICLK High (Note 3)
9 LOCK High to ALE Low
T_La
Ta
3Ta
19
ns
b2
ns
20
ns
t_SU-WT-ICLK
10 WAIT Low after ICLK Rising to Extend Cycle
(Note 4)
(MAX(n_DW n_IWb1))TaT_Ha
b22 ns
t_H-WT-ICLK
t_H-LK-ICLK
t_PD-AD-ALE
t_SU-WT-ALEf
11 WAIT High after ICLK Rising (Notes 2 4)
12 LOCK Rising after ICLK High
13 AD to ALE Falling after LOCK Rising
(MAX(n_DW n_IWb1))TaT_Ha
2
ns
(MAX(n_DW n_IWb1)a1)TaT_Ha
b20 ns
T_Ha
2
ns
Ta
b33
ns
14 WAIT Low before ALE Falling to Extend Cycle
23
ns
Note 1 All parameters are individually tested and guaranteed Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results
Note 2 The maximum value for this parameter is the lastest WAIT can be removed without adding an additional T-state The formula assumes a minimum
externally generated wait of one T-state
Note 3 If t_SU-LK-ICLK is not met the maximum time from LOCK low till no more local accesses is (MAX(n_DW n_IWb1)a3)T
Note 4 The formula(s) apply to a 2 T-state instruction For a 3 T-state instruction add one T-state for a 4 T-state instruction add two T-states
106