DP8344B Datasheet, PDF (111/184 Pages) National Semiconductor (TI) – Biphase Communications ProcessorㅡBCP

5 0 Device Specifications (Continued)
TABLE 5-14 Latched Read of PC RIC (Note 1)
Symbol
ID
Parameter
Formula
Min
Max
Units
t_SU-RRR-CO
1
RAE REM-RD Falling before CLK-OUT Rising
22
ns
t_H-RRR-X
2
RAE REM-RD Rising after XACK Rising
0
ns
t_SU-CMD-RRR
3
CMD Valid before RAE REM-RD Falling
0
ns
t_H-CMD-RRR
4
CMD Invalid after RAE REM-RD Falling
Ta
26
ns
t_PD-RRR-X
5
RAE REM-RD Falling to XACK Falling
26
ns
t_PD-Xf-LCLr
6
XACK Falling to LCL Rising
(n_LWa1)Ta
b5
ns
t_PD-LCL-X
7
LCL Rising to XACK Rising
2Ta
b10
8
ns
t_PD-Xr-LCLf
8
XACK Rising to LCL Falling
Ta
b11
11
ns
t_AZ-A-LCL
9
A Disabled before LCL Rising
T_La
b18
ns
t_ZA-LCL-A
10
A Enabled after LCL Falling
T_Ha
b12
ns
t_PC-LCL-PC
11
LCL Rising to AD (PC) Valid
Ta
20
ns
t_PD-PC-X
12
AD (PC) Valid before XACK Rising
Ta
b22
ns
t_PD-X-PC
13
XACK Rising to AD (PC) Invalid
T_Ha
0
ns
t_W-PC
14
AD (PC RIC) Valid
TaT_Ha
b12
ns
Note 1 All parameters are individually tested and guaranteed Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results
FIGURE 5-14 Latched Read of PC RIC
111
TL F 9336 – 68