SCAN921025 Datasheet, PDF (9/21 Pages) National Semiconductor (TI) – 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST

AC Timing Diagrams and Test Circuits
FIGURE 2. “Worst Case” Serializer ICC Test Pattern
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FIGURE 3. “Worst Case” Deserializer ICC Test Pattern
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FIGURE 4. Serializer Bus LVDS Output Load and Transition Times
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FIGURE 5. Deserializer CMOS/TTL Output Load and Transition Times
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FIGURE 6. Serializer Input Clock Transition Time
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