LP2994 Datasheet, PDF (9/15 Pages) National Semiconductor (TI) – DDR Termination Regulator

Component Selection (Continued)
dielectric types have poor capacitance characteristics as a
function of voltage and temperature. Because of the typically
low value of capacitance it is recommended to use ceramic
capacitors in parallel with another capacitor such as an
aluminum electrolytic. A dielectric of X5R or better is recom-
mended for all ceramic capacitors.
Hybrid - Several hybrid capacitors such as OS-CON and SP
are available from several manufacturers. These offer a
large capacitance while maintaining a low ESR. These are
the best solution when size and performance are critical,
although their cost is typically higher than other capacitors.
Thermal Dissipation
Since the LP2994 is a linear regulator any current flow from
V_TT will result in internal power dissipation generating heat.
To prevent damaging the part from exceeding the maximum
allowable junction temperature, care should be taken to
derate the part dependent on the maximum expected ambi-
ent temperature and power dissipation. The maximum allow-
able internal temperature rise (T_Rmax) can be calculated
given the maximum ambient temperature (T_Amax) of the
application and the maximum allowable junction temperature
(T_Jmax).
T_Rmax = T_Jmax − T_Amax
From this equation, the maximum power dissipation (P_D) of
the part can be calculated:
P_Dmax = T_Rmax / θ_JA
The θ_JA of the LP2994 will be dependent on several vari-
ables: the package used; the thickness of copper; the num-
ber of vias and the airflow. For instance, the θ_JA of the SO-8
is 163˚C/W with the package mounted to a standard 8x4
2-layer board with 1oz. copper, no airflow, and 0.5W dissi-
pation at room temperature. This value can be reduced to
151.2˚C/W by changing to a 3x4 board with 2 oz. copper that
is the JEDEC standard. Figure 3 shows how the θ_JA varies
with airflow for the two boards mentioned.
20045928
FIGURE 3. θ_JA vs Airflow
Additional improvements can be made by the judicious use
of vias to connect the part and dissipate heat to an internal
ground plane. Using larger traces and more copper on the
top side of the board can also help. With careful layout, it is
possible to reduce the θ_JA further than the nominal values
shown in Figure 3.
Optimizing the θ_JA and placing the LP2994 in a section of a
board exposed to lower ambient temperature allows the part
to operate with higher power dissipation. The internal power
dissipation can be calculated by summing the three main
sources of loss: output current at V_TT, either sinking or
sourcing, and quiescent current at AVIN and V_DDQ. During
the active state (when Shutdown is not held low) the total
internal power dissipation can be calculated from the follow-
ing equations:
where,
P_D = P_AVIN + P_VDDQ + P_VTT
P_AVIN = I_AVIN x V_AVIN
P_VDDQ = V_VDDQ x I_VDDQ = V_VDDQ2 x R_VDDQ
To calculate the maximum power dissipation at V_TT, both
sinking and sourcing current conditions at V_TT need to be
examined. Although only one equation will add into the total,
V_TT cannot source and sink current simultaneously.
P_VTT = V_VTT x I_LOAD (Sinking)
or
P_VTT = ( V_PVIN - V_VTT) x I_LOAD (Sourcing)
The power dissipation of the LP2994 can also be calculated
during the shutdown state. During this condition the output
V_TT will tri-state, therefore that term in the power equation
will disappear as it cannot sink or source any current (leak-
age is negligible). The only losses during shutdown will be
the reduced quiescent current at AVIN and the constant
impedance that is seen at the V_DDQ pin.
P_D = P_AVIN + P_VDDQ
Where,
P_AVIN = I_AVIN x V_AVIN
P_VDDQ = V_VDDQ x I_VDDQ = V_VDDQ2 x R_VDDQ
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