LP2994 Datasheet, PDF (1/15 Pages) National Semiconductor (TI) – DDR Termination Regulator

May 2002
LP2994
DDR Termination Regulator
General Description
The LP2994 regulator is designed to provide a linear solution
to meet the JEDEC SSTL-2 and SSTL-3 specifications (Se-
ries Stub Termination Logic) for active termination of DDR-
SDRAM. The device utilizes an internal operational amplifier
to provide linear regulation of V_TT without the need for
expensive external components. The output stage prevents
shoot through while delivering 1.5A continuous current and
maintaining excellent load regulation. The LP2994 also in-
corporates an active low shutdown pin to tri-state the output
during Suspend To Ram (STR) states.
Patents Pending
Features
n Source and sink current
n Low external component count
n Independent analog and power rails
n Linear topology
n Small package SO-8
n Low cost and easy to use
n Shutdown pin
Applications
n SSTL-2
n SSTL-3
n DDR-SDRAM Termination
n DDR-II Termination
Typical Application Circuit
FIGURE 1. SSTL-2 V_TT Termination
20045904
© 2002 National Semiconductor Corporation DS200459
www.national.com