LMH0340_08 Datasheet, PDF (9/24 Pages) National Semiconductor (TI) – 3G, HD, SD, DVB-ASI SDI Serializer and Driver with LVDS Interface

practicable. The output driver automatically adjusts its slew
rate depending on the input datarate so that it will be in com-
pliance with SMPTE 259M, SMPTE292M or SMPTE 424M as
appropriate. In addition to output amplitude and rise/fall time
specifications, the SMPTE specs require that SDI outputs
meet an Output Return Loss (ORL) specification. There are
parasitic capacitances that will be present both at the output
pin of the device and on the application printed circuit board.
To optimize the return loss implement a series network com-
prised of a parallel inductor and resistor. The actual values for
these components will vary from application to application,
but the typical interface circuit shows values that would be a
good starting point. Figure 5 shows an equivalent output cir-
cuit for the LMH0340 / LMH0040 / LMH0070. The collectors
present a high impedance current source. The external 75Ω
resistors will provide the back termination resistance as well
as converting the current to a voltage – with the addition of
the termination resistance at the load, there will be an overall
output resistance of 37.5Ω, which in conjunction with the 24-
mA current source will develop the 800mV swings called for
in the standard.
30017011
FIGURE 6. SDI Output Return Loss (EVK Example)
The amplitude of the output is guaranteed to be compliant with
SMPTE specifications if the specified value of R_SET resistor is
used, however if the designer wishes to change the output
amplitude, there are two methods by which this can be done.
By changing the value of resistor connected to the R_SET pin,
the output amplitude will be adjusted.
30017007
FIGURE 5. Simplified SDI Output Circuit
Care must be taken in the layout of the output circuitry to meet
SMPTE return loss specifications as any parasitic
impedances or transmission line discontinuities will result in
reflections which will adversely affect the output return loss.
For more details on how to get good output return loss, please
refer to the application note “Successful design with the
FPGA-Attach SER/DES”.
30017012
FIGURE 7. Output Voltage vs. R_SET
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