LMH0340_08 Datasheet, PDF (20/24 Pages) National Semiconductor (TI) – 3G, HD, SD, DVB-ASI SDI Serializer and Driver with LVDS Interface

ADD
'h
30
Name
CLK_Delay
Bits
Field
R/W Default Description
The three msbs from this register are used to insert a programmable delay into the TXCLK path,
if the host FPGA does not provide adequate setup and hold times for the SER, this register can
be used to shift the window in 125ps increments.
7:5
TCLK Delay
r/w
011'b
000'b is minimum delay setting, 111'b is
maximum delay setting, each step is
approx 125ps
4:0
Reserved
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