LMH0340_08 Datasheet, PDF (14/24 Pages) National Semiconductor (TI) – 3G, HD, SD, DVB-ASI SDI Serializer and Driver with LVDS Interface

FIGURE 13. Typical SMPTE Application Circuit
30017006
TYPICAL LMH0050 CML APPLICATIONS CIRCUIT
A typical application circuit for the LMH0050 is shown in Fig-
ure 14.
The TX interface between the host FPGA and the SER is
composed of a 5-bit LVDS Data bus and its LVDS clock. This
is a point-to-point interface and the SER includes on-chip 100
terminations. Pairs should be of equal length to minimize any
skew impact. The LVDS clock (TXCLK) uses both edges to
transfer the data.
An SMBus is also connected from the host FPGA to the SER.
If the SMBus is shared, a chip select signal is used to select
the device being addressed. The SCLK and SDA signals re-
quire a pull up resistor. The SMB_CS is driven by a GPO
signal from the FPGA. Depending on the FPGA I/O it may also
require a pull up unless it is a push / pull output.
Depending upon the application, several other GPIO signals
maybe used. This includes the DVB_ASI and RESET input
signals. If these pins are not used, then must be tied off to the
desired state. The LOCK signal maybe used to monitor the
SER. If it is unused, leave the pin as a NC (or route to a test
point).
The LMH0050 SER includes a CML cable driver. This is a
differential driver, and includes internal 50 Ω pull up resistors
to the 2.5V rail. The output voltage amplitude of the cable
driver is set by the R_SET resistor. The R_SET resistor recom-
mended value for the LMH0050 is 9.1KΩ. It is intended to
drive 100 Ω differential pairs or twisted pair cables.
The PLL loop filter is external for the SER. A capacitor is con-
nected in series to a resistor between the LF_CP and LF_REF
pins. Typical values are 500 Ω and 0.1 µF.
There are several configuration pins that requiring setting to
the proper level. The RSVD_H pins should be pulled High to
the 3.3V rail with a 5 kΩ resistor. Depending upon the appli-
cation the DVB_ASI pin may be tied off or driven.
There are three supply connections (see By Pass discussion
and also Pin Descriptions for recommendations). The two
main supplies are the 3.3V rail and the 2.5V rail. There is also
a 3.3V connection for the PLL circuitry.
There are multiple Ground connections for the device. The
main ground connection for the SER is through the large cen-
ter DAP pad. This must be connected to ground for proper
device operation. In addition, multiple other inputs are re-
quired to be connected to ground as show in the figure and
listed in the Pin Description table.
www.national.com
14