LMC660EP Datasheet, PDF (9/15 Pages) National Semiconductor (TI) – CMOS Quad Operational Amplifier

Application Hints (Continued)
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C_S consists of the amplifier’s input capacitance plus any stray capacitance
from the circuit board and socket. C_F compensates for the pole caused by
C_S and the feedback resistors.
FIGURE 2. General Operational Amplifier Circuit
Using the smaller capacitors will give much higher band-
width with little degradation of transient response. It may be
necessary in any of the above cases to use a somewhat
larger feedback capacitor to allow for unexpected stray ca-
pacitance, or to tolerate additional phase shifts in the loop, or
excessive capacitive load, or to decrease the noise or band-
width, or simply because the particular circuit implementa-
tion needs more feedback capacitance to be sufficiently
stable. For example, a printed circuit board’s stray capaci-
tance may be larger or smaller than the breadboard’s, so the
actual optimum value for C_F may be different from the one
estimated using the breadboard. In most cases, the values
of C_F should be checked on the actual circuit, starting with
the computed value.
CAPACITIVE LOAD TOLERANCE
Like many other op amps, the LMC660EP may oscillate
when its applied load appears capacitive. The threshold of
oscillation varies both with load and circuit gain. The con-
figuration most sensitive to oscillation is a unity-gain follower.
See Typical Performance Characteristics.
The load capacitance interacts with the op amp’s output
resistance to create an additional pole. If this pole frequency
is sufficiently low, it will degrade the op amp’s phase margin
so that the amplifier is no longer stable at low gains. As
shown in Figure 3, the addition of a small resistor (50Ω to
100Ω) in series with the op amp’s output, and a capacitor (5
pF to 10 pF) from inverting input to output pins, returns the
phase margin to a safe value without interfering with lower-
frequency circuit operation. Thus larger values of capaci-
tance can be tolerated without oscillation. Note that in all
cases, the output will ring heavily when the load capacitance
is near the threshold for oscillation.
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FIGURE 3. Rx, Cx Improve Capacitive Load Tolerance
Capacitive load driving capability is enhanced by using a pull
up resistor to V⁺ (Figure 4). Typically a pull up resistor
conducting 500 µA or more will significantly improve capaci-
tive load responses. The value of the pull up resistor must be
determined based on the current sinking capability of the
amplifier with respect to the desired output swing. Open loop
gain of the amplifier can also be affected by the pull up
resistor (see Electrical Characteristics).
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FIGURE 4. Compensating for Large Capacitive Loads
with a Pull Up Resistor
PRINTED-CIRCUIT-BOARD LAYOUT
FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate
with less than 1000 pA of leakage current requires special
layout of the PC board. When one wishes to take advantage
of the ultra-low bias current of the LMC662, typically less
than 0.04 pA, it is essential to have an excellent layout.
Fortunately, the techniques for obtaining low leakages are
quite simple. First, the user must not ignore the surface
leakage of the PC board, even though it may sometimes
appear acceptably low, because under conditions of high
humidity or dust or contamination, the surface leakage will
be appreciable.
To minimize the effect of any surface leakage, lay out a ring
of foil completely surrounding the LMC660EP’s inputs and
the terminals of capacitors, diodes, conductors, resistors,
relay terminals, etc. connected to the op-amp’s inputs. See
Figure 5. To have a significant effect, guard rings should be
placed on both the top and bottom of the PC board. This PC
foil must then be connected to a voltage which is at the same
voltage as the amplifier inputs, since no leakage current can
flow between two points at the same potential. For example,
a PC board trace-to-pad resistance of 10¹²â„¦, which is nor-
mally considered a very large resistance, could leak 5 pA if
the trace were a 5V bus adjacent to the pad of an input. This
would cause a 100 times degradation from the LMC660EP’s
actual performance. However, if a guard ring is held within
5 mV of the inputs, then even a resistance of 10¹¹â„¦ would
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