DS92LV1212 Datasheet, PDF (9/13 Pages) National Semiconductor (TI) – 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery

AC Timing Diagrams and Test Circuits (Continued)
FIGURE 7. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays
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FIGURE 8. Deserializer PLL Lock Time from SyncPAT
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