DS92LV1212 Datasheet, PDF (12/13 Pages) National Semiconductor (TI) – 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery

Deserializer Pin Description (Continued)
Pin Name
RCLK_R/F
RI+
RI−
PWRDN
LOCK
RCLK
REN
DVCC
DGND
AVCC
AGND
REFCLK
I/O
No.
Description
I
2
Recovered Clock Rising/Falling strobe select. TTL level input.
Selects RCLK active edge for strobing of ROUT data. High
selects rising edge. Low selects falling edge.
I
5
+ Serial Data Input. Non-inverting Bus LVDS differential input.
I
6
− Serial Data Input. Inverting Bus LVDS differential input.
I
7
Powerdown. TTL level input. PWRDN driven low shuts down the
PLL.
O
10
LOCK goes low when the Deserializer PLL locks onto the
embedded clock edge. CMOS level output. Totem pole output
structure, does not directly support wire OR connection.
O
9
Recovered Clock. Parallel data rate clock recovered from
embedded clock. Used to strobe ROUT, CMOS level output.
I
8
Output Enable. TTL level input. TRI-STATEs ROUT0–ROUT9,
LOCK and RCLK when driven low.
I
21, 23
Digital Circuit power supply.
I
14, 20, 22
Digital Circuit ground.
I
4, 11
Analog power supply (PLL and Analog Circuits).
I
1, 12, 13
Analog ground (PLL and Analog Circuits).
I
3
Use this pin to supply a REFCLK signal for the internal PLL
frequency.
Truth Table
RI
X
Z
DATA (0–9)
DATA (0–9)
SYNC PTRN
DATA (0–9)
DATA (0–9)
RI−
X
Z
DATA (0–9)*
DATA (0–9)*
SYNC PTRN*
DATA (0–9)*
DATA (0–9)*
RCLK_R/F
X
X
X
X
X
1
0
REFCLK
SYSTEM CLK
SYSTEM CLK
SYSTEM CLK
SYSTEM CLK
SYSTEM CLK
SYSTEM CLK
SYSTEM CLK
REN
X
X
0
0
1
1
1
PWRDN
0
X
1
1
1
1
1
RCLK
Z
Z
Z
Z
CLK
L
K
LOCK
Z
Z
L →Z **
H →PLL **
1
0
0
ROUT (0–9)
Z
Z
Z
Z
SYNC PTRN
DATA
DATA
* Inverted
**If the Rx is locked when REN goes low the LOCK* output will go Tri-state on the rising edge of REFCLK. If the Rx is not locked when REN goes low the LOCK*
output will remain active. It will be high as the Rx is not locked but should the Rx attain lock the LOCK* output will go low to indicate lock.
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