DS92LV1212 Datasheet, PDF (7/13 Pages) National Semiconductor (TI) – 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery

AC Timing Diagrams and Test Circuits
FIGURE 1. “Worst Case” Deserializer ICC Test Pattern
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FIGURE 2. Deserializer CMOS/TTL Output Load and Transition Times
FIGURE 3. Serializer Delay
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FIGURE 4. Deserializer Delay
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